1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device suitable for a metal oxide field effect transistor (MOSFET) or an insulated gate bipolar transistor (IGBT).
2. Description of the Related Art
When an inverter circuit is composed of a MOSFET or an IGBT, the inverter circuit has a mode in which a current flows in a reverse direction due to inductance of a motor or the like used as a load under the condition that switching devices are in an off state. When an inverter circuit is composed of junction field effect transistors (JFETs), it is therefore necessary that a diode for causing the current to flow back be connected in inverse parallel relationship with each JFET in the inverter circuit. This results in an increase in the cost. In addition, the downsizing of a package is limited. Therefore, a MOSFET or an IGBT is used generally as a switching device of an inverter.
On the other hand, silicon carbide (SiC) has a breakdown electric field than larger by approximately 10 times than that of silicon (Si), and is a material allowing a high voltage resistance drift layer to have a small thickness and a high concentration. Losses of MOSFETs using SiC are lower than those of MOSFETs using Si. The MOSFETs using Sic have been expected as destruction-resistant devices. Especially, a U-shaped metal oxide semiconductor field effect transistor (UMOSFET) using a sidewall of a trench as a channel has an advantage to shrink the device size. Power MOSFETs using Si have been manufactured. Each of the power MOSFETs has a structure capable of reducing an on-state voltage. When the UMOSFET uses SiC, the UMOSFET has a large breakdown electric field. Therefore, a large electric field may occur on a gate oxide film formed on a corner portion of a trench provided in the UMOSFET, and the UMOSFET may be broken. To avoid this problem, a technique for preventing an electric field from being concentrated is used. FIG. 19 schematically shows a cross sectional structure of a conventional, typical UMOSFET using SiC. In the example shown in FIG. 19, a region for relaxing the concentration of an electric field on an oxide film is formed around a bottom portion of a trench. In FIG. 19, reference numeral 10 denotes an N+ type wafer; 11, an N− type drift layer; 12, a P type body; 13, an N+ type source layer; 14, a P+ type region for forming a contact with the P type body; 17, a gate oxide film; 31, a drain electrode; 32, a silicide electrode forming an ohmic contact between the N+ type source layer 13 and the P+ region 14; 33, a source electrode; and 34, a gate electrode. The UMOSFET shown in FIG. 19 has a P+ type region 16 provided around the bottom portion of the trench. The P+ type region 16 is adapted to relax the concentration of the electric field. The UMOSFET has a structure capable of preventing an excessive electric field from being generated on the oxide film formed on a corner portion of the trench. Such a structure is disclosed in, for example, JP-A-H10-98188.